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ICs for Communications
Two Channel Codec Filter with IOM(R)-2 Interface (IOM(R)-2 - SICOFI(R)-2) PEB 2265 Version 1.1
Preliminary Data Sheet 1997-07-01
T2265-XV11-P1-7600
PEB 2265 Revision History: Previous Version: Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) Current Version: 1997-07-01
Edition 1997-07-01 HL TS, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 2265
Table of Contents 1 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.6
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Common Pins for all Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Specific Pins for Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Specific Pins for Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 IOM(R)-2 - SICOFI(R)-2 Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 IOM(R)-2 - SICOFI(R)-2 Signal Flow Graph (for either channel) . . . . . . . . . .12 Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Receive Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 IOM(R)-2 - SICOFI(R)-2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 IOM(R)-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 IOM(R)-2 Interface Timing for 16 voice channels (per 8 kHz frame) . . . . . .15 IOM(R)-2 Interface Timing (DCL = 4096 kHz, MODE = 1, per 8 kHz frame) 15 IOM(R)-2 Interface Timing (DCL = 2048 kHz, MODE = 0) . . . . . . . . . . . . . .16 IOM(R)-2 Time-Slot Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Programming the IOM(R)-2 - SICOFI(R)-2 . . . . . . . . . . . . . . . . . . . . . . . . . .18 Types of Monitor Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 IOM(R)-2 - SICOFI(R)-2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 SOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 XOP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 COP - Write Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 SOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 XOP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 COP - Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Example for a Mixed Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CR1 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 CR2 Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 CR3 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 CR4 Configuration Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 XOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 XR1 Extended Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 XR2 Extended Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 XR3 Extended Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 XR4 Extended Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3 1997-07-01
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Table of Contents 3.7 3.8 3.8.1 3.8.2 3.8.3 3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 4 4.1 5 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.2 5.2.3 5.3 5.4 5.5 5.6 5.7 5.8 5.8.1 5.8.2 5.9 5.10 6 6.1 6.2 6.3 6.4 6.5 6.6 6.6.1 6.6.2
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IOM(R)-2 Interface Command/Indication Byte . . . . . . . . . . . . . . . . . . . . . . .38 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 RESET (Basic setting mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Programmable Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Impedance Matching Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Transhybrid Balancing (TH) Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Filters for Frequency Response Correction . . . . . . . . . . . . . . . . . . . . . . . .43 Amplification/Attenuation -Filters AX1, AX2, AR1, AR2 . . . . . . . . . . . . . .44 Amplification/Attenuation Receive (AR1, AR2)-Filter . . . . . . . . . . . . . . . .44 Amplification/Attenuation Transmit (AX1, AX2)-Filter . . . . . . . . . . . . . . . .44 QSICOS Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 QSICOS Supports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Receive: reference frequency 1 kHz, input signal level 0 dBm0 . . . . . . . .48 Transmit: reference frequency 1 kHz, input signal level 0 dBm0 . . . . . . .48 Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Group Delay absolute values: Input signal level 0 dBm0 . . . . . . . . . . . . .49 Group Delay Distortion transmit: Input signal level 0 dBm0 . . . . . . . . . . .49 Group Delay Distortion receive: Input signal level 0dBm0 . . . . . . . . . . . .50 Out-of-Band Signals at Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Out-of-Band Signals at Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Out of Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . . . .52 Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Gain Tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Total Distortion Measured with Sine Wave . . . . . . . . . . . . . . . . . . . . . . . .53 Total Distortion Measured with Noise According to CCITT . . . . . . . . . . . .54 Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 IOM(R)-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4 MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2 MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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Table of Contents 6.7 6.7.1 6.7.2 6.8 6.8.1 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.2.1 7.2.2 7.3 8 8.1 8.1.1 8.1.2 8.2 8.3 9
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IOM(R)-2 Command/Indication Interface Timing . . . . . . . . . . . . . . . . . . . . .61 4 MHz Operation Mode (Mode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2 MHz Operation Mode (Mode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Detector Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 IOM(R)-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . .64 Monitor Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Monitor Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 State Diagram of the IOM(R)-2 - SICOFI(R)-2 Monitor Transmitter . . . . . . . .66 State Diagram of the IOM(R)-2 - SICOFI(R)-2 Monitor Receiver . . . . . . . . . .67 Monitor Channel Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Identification Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 IOM(R)-2 Interface Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . .69 Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 The TAP-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Level Metering Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Programming the IOM(R)-2 - SICOFI(R)-2 Tone Generators . . . . . . . . . . . .76 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
IOM(R), IOM (R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983.
Semiconductor Group
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PEB 2265
Overview 1 Overview
The two Channel Codec Filter PEB 2265 IOM-2 - SICOFI-2 is the logic continuation of a well-established family of Siemens Codec-Filter-ICs. The IOM-2 - SICOFI-2 is a fully integrated PCM codec and filter fabricated in low power 1 m CMOS technology for applications in digital communication systems. Based on an advanced digital filter concept, the PEB 2265 provides excellent transmission performance and high flexibility. The new filter concept (second generation) lends to a maximum of independence between the different filter blocks. Each filter block can be seen like an one to one representative of the corresponding network element. Only very few external components are needed, to complete the functionality of the IOM-2 - SICOFI-2. The internal level accuracy is based on a very accurate bandgap reference. The frequency behavior is mainly determined by digital filters, which do not have any fluctuations. As a result of the new ADC and DAC concepts linearity is only limited by second order parasitic effects. Although the device works with only one single 5-V supply there is a very good dynamic range available.
Semiconductor Group
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Two Channel Codec Filter with IOM(R)-2 Interface IOM(R)-2 - SICOFI(R)-2
PEB 2265
1.1
Features
* Single chip CODEC and FILTER to handle two CO- or PABX-channels * Specification according to relevant CCITT, EIA and LSSGR recommendations * Digital signal processing technique * Programmable interface optimized to current feed SLICs and transformer solutions P-MQFP-64-1-2 * Four pin serial IOM-2 Interface * Single power supply 5 V * Advanced low power 1m analog CMOS technology * Standard 64-pin P-MQFP-64 package * High performance Analog to Digital Conversion * High performance Digital to Analog Conversion * Programmable digital filters to adapt the transmission behavior especially for - AC impedance matching - transhybrid balancing - frequency response - gain * Advanced test capabilities - all digital pins can be tested within a boundary scan scheme (IEEE 1149.1) - five digital loops - four analog loops - two programmable tone generators per channel * Comprehensive development platform available - software for automatic filter coefficient calculation - QSICOS - Hardware development board - STUT 2465
Type PEB 2265 H V1.1
Semiconductor Group
Ordering Code on request
7
Package P-MQFP-64-1-2
1997-07-01
PEB 2265
Overview 1.2 Pin Configuration (top view)
N.C. N.U.I. N.U.I. N.U.I. N.U.IO.
3 3 3 2 2 2 2 2 2 23 2 2 2 1 18 1 210987654 2109 7 1 6 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 15 14 13 12
1 1
N.U.IO. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.U.IO.
10
IOM2-SICOFI-2
9 8 7 6
5
4 3 2
48 1 4 5 5 5 5 5 5 5 5 58 5 6 6 6 63 6 901234567 9012 4
N.U.IO. N.U.I. N.U.I. N.U.I.
Figure 1
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Overview 1.3 1.3.1 Table 1 Pin No. 23 58 Symbol VDDD GNDD Input (I) Function Output (O) I I + 5 V supply for the digital circuitry1) Ground Digital, not internally connected to GNDA 1, 2 or GNDA (pin 6 and pin 11). All digital signals are referred to this pin + 5 V Analog supply voltage for channel 1 and 21) + 5 V Analog supply voltage1) Ground Analog, not internally connected to GNDD or GNDA1,2 IOM-2: Frame synchronization clock, 8 kHz IOM-2: Data clock, 2048 kHz or 4096 kHz depending on MODE IOM-2: Data upstream, open drain output IOM-2: Data downstream, input Reset input - forces the device to the default mode, active high IOM-2: Mode Selection IOM-2: Time slot selection pin 0 IOM-2: Time slot selection pin 1 Boundary scan: Test Clock Boundary scan: Test Mode Select Boundary scan: Test Data Input Boundary scan: Test Data Output Loop/Ground Key Multiplexing output 0 for channel 1, 2 Reference voltage for channel 1 and 2, has to be connected via a 220 nF cap. to ground None Usable Input, tie directly to Digital Ground Pin Definition and Functions Common Pins for all Channels
40 9 6,11 27 26 25 24 22 57 60 59 56 55 54 53 28 41
VDDA12 VDDA GNDA FSC DCL DU DD RESET MODE TSS0 TSS1 TCK TMS TDI TDO LGKM0 VH12
I I I I I O I I I I I I I I O O I/O I
18,19,20 N.U.I. 61,62,63
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PEB 2265
Overview Table 1 Pin No. 1,16 17,64 (cont'd) Symbol N.U.IO. Input (I) Function Output (O) I/O None Usable Input/Output, tie via a Pull-Down-Resistor to Digital Ground not connected
2,3,4,5,7 N.C. 8,10,12 13,14,15 21
1)
A 100 nF cap. should be used for blocking these pin.
1.3.2 Table 2
Specific Pins for Channel 1
Pin No. Symbol 38 GNDA1
Input (I) Output (O) I
Function Ground Analog for channel 1, not internally connected to GNDD or GNDA2 or GNDA (pin 6 and pin 11) Analog voice (voltage) input for channel 1 Analog voice (voltage) output for channel 1 Signaling indication input pin 0 for channel 1 Signaling indication input pin 1 for channel 1 Signaling indication input pin 2 for channel 1 Signaling command output pin 0 for channel 1 Signaling command output pin 1 for channel 1 Signaling command output pin 2 for channel 1 Bi-directional signal. Command indication pin 0 for channel 1 Bi-directional signal. Command indication pin 1 for channel 1
39 37 31 30 29 36 35 34 33 32
VIN1 VOUT1 SI1_0 SI1_1 SI1_2 SO1_0 SO1_1 SO1_2 SB1_0 SB1_1
I O I I I O O O I/O I/O
Semiconductor Group
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PEB 2265
Overview 1.3.3 Table 3 Pin No. Symbol 43 GNDA2 Input (I) Output (O) I Function Ground Analog for channel 2, not internally connected to GNDD or GNDA1 or GNDA (pin 6 and pin 11) Analog voice (voltage) input for channel 2 Analog voice (voltage) output for channel 2 Signaling indication input pin 0 for channel 2 Signaling indication input pin 1 for channel 2 Signaling indication input pin 2 for channel 2 Signaling command output pin 0 for channel 2 Signaling command output pin 1 for channel 2 Signaling command output pin 2 for channel 2 Bi-directional signal. command indication pin 0 for channel 2 Bi-directional signal. command indication pin 1 for channel 2 Specific Pins for Channel 2
42 44 50 51 52 45 46 47 48 49
VIN2 VOUT2 SI2_0 SI2_1 SI2_2 SO2_0 SO2_1 SO2_2 SB2_0 SB2_1
I O I I I O O O I/O I/O
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PEB 2265
IOM(R)-2 - SICOFI(R)-2 Principles 2 IOM(R)-2 - SICOFI(R)-2 Principles
The change from 2 m to 1 m CMOS process requires new concepts in the realization of the analog functions. High performance (in the terms of gain, speed, stability ...) 1 m CMOS devices can not withstand more than 5.5 V of supply voltage. On that account the negative supply voltage VSS of the previous SICOFIs will be omitted. This is a benefit for the user but it makes a very high demand on the analog circuitry. ADC and DAC are changed to Sigma-Delta-concepts to fulfill the stringent requirements on the dynamic parameters. Using 1 m CMOS does not only lend to problems - it is the only acceptable solution in terms of area and power consumption for the integration of more then two SICOFI channels on a single chip. It is rather pointless to implement 2 codec-filter-channels on one chip with pure analog circuitry. The use of a DSP-concept (the SICOFI and the SICOFI-2-approach) for this function seems to be a must for an adequate two channel architecture. 2.1 IOM(R)-2 - SICOFI(R)-2 Signal Flow Graph (for either channel)
Figure 2
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PEB 2265
IOM(R)-2 - SICOFI(R)-2 Principles 2.1.1 Transmit Path
The analog input signal has to be DC-free connected by an external capacitor because there is an internal virtual reference ground potential. After passing a simple antialiasing prefilter (PREFI) the voice signal is converted to a 1-bit digital data stream in the Sigma-Delta-converter. The first downsampling steps are done in fast running digital hardware filters. The following steps are implemented in the micro-code which has to be executed by the central Digital Signal Processor. This DSP-machine is able to handle the workload for all two channels. At the end the fully processed signal (flexibly programmed in many parameters) is transferred to the IOM-2 interface in a PCM-compressed signal representation. 2.1.2 Receive Path
The digital input signal is received via the IOM-2 interface. Expansion, PCM-law-pass-filtering, gain correction and frequency response correction are the next steps which are done by the DSP-machine. The upsampling interpolation steps are again processed by fast hardware structures to reduce the DSP-workload. The upsampled 1-bit data stream is then converted to an analog equivalent which is smoothed by a POST-Filter (POFI). As the signal VOUT is also referenced to an internal virtual ground potential, an external capacitor is required for DC-decoupling. 2.1.3 Loops
There are two loops implemented. The first is to generate the AC-input impedance (IM) and the second is to perform a proper hybrid balancing (TH). A simple extra path IM2 (from the transmit to the receive path) supports the impedance matching function. 2.1.4 Test Features
There are four analog and five digital test loops implemented in the IOM-2 - SICOFI-2. For special tests it is possible to "Cut Off" the receive and the transmit path at two different points.
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IOM(R)-2 - SICOFI(R)-2 Principles 2.2 IOM(R)-2 - SICOFI(R)-2 Block Diagram
HW-Filter
HW-Filter
Analog out Analog in
DAC ADC
DSP
DAC ADC
Analog out Analog in
Command Indication
Signaling
IOM2-Interface
Signaling
Command Indication
IOM2-Bus
iom3.wmf
Figure 3 The IOM-2 - SICOFI-2 bridges the gap between analog and digital voice signal transmission in modern telecommunication systems. High performance oversampling Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC) provide the required conversion accuracy. Analog antialiasing prefilters (PREFI) and smoothing postfilters (POFI) are included. The connection between the ADC and the DAC (with high sampling rate) and the DSP, is done by specific Hardware Filters, for filtering like interpolation and decimation. The dedicated Digital Signal Processor (DSP) handles all the algorithms necessary e.g. for PCM bandpass filtering, sample rate conversion and PCM companding. The IOM-2 Interface handles digital voice transmission, IOM-2 - SICOFI-2 feature control and transparent access to the IOM-2 - SICOFI-2 command and indication pins. To program the filters, precalculated sets of coefficients are downloaded from the system to the on chip coefficient ram (CRAM). 2.3 IOM(R)-2 Interface
The IOM-2 Interface consists of two data lines and two clock lines. DU (data upstream) carries data from the IOM-2 - SICOFI-2 to a master device. This master device performs the interface between the PCM-backplane, the Controller and up to 24 IOM-2 - SICOFI-2's. DD (data downstream) carries data from the master device to the IOM-2-SICOF-2. A frame synchronization clock signal (8 kHz, FSC) as well as a data clock signal (2048 kHz or 4096 kHz DCL) has to be supplied to the IOM-2 - SICOFI-2. The IOM-2 - SICOFI-2 handles data as described in the IOM-2 specification for analog devices.
Semiconductor Group
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IOM(R)-2 - SICOFI(R)-2 Principles 2.3.1 IOM(R)-2 Interface Timing for 16 voice channels (per 8 kHz frame)
Figure 4 2.3.2 IOM(R)-2 Interface Timing (DCL = 4096 kHz, MODE = 1, per 8 kHz frame)
Figure 5
Semiconductor Group
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IOM(R)-2 - SICOFI(R)-2 Principles 2.3.3 IOM(R)-2 Interface Timing (DCL = 2048 kHz, MODE = 0)
Figure 6 2.3.4 IOM(R)-2 Time Slot Selection
The two channels (1 and 2) of the IOM-2 - SICOFI-2 can be assigned to 4 time slots by pin-strapping the pins TSS0 and TSS1 (TS0, TS2, TS4, TS6). The IOM-2 operating mode is selected by the MODE pin. Table 4 TSS1 0 0 1 1 0 0 1 1 TSS0 0 1 0 1 0 1 0 1 MODE 1 1 1 1 0 0 0 0 IOM(R)-2 Operating Mode Time slot 0; DCL= 4096 kHz Time slot 2; DCL= 4096 kHz Time slot 4; DCL= 4096 kHz Time slot 6; DCL= 4096 kHz Time slot 0; DCL= 2048 kHz Time slot 2; DCL= 2048 kHz Time slot 4; DCL= 2048 kHz Time slot 6; DCL= 2048 kHz
16 1997-07-01
Semiconductor Group
PEB 2265
IOM(R)-2 - SICOFI(R)-2 Principles Each IOM time slot contains 2 voice channels (A and B). Those two voice channels share a common IOM-Monitor-byte as well as a common C/I-byte. The AD-bit in the Monitor command defines which of the two voice channels should be affected (programmed). (For more information on IOM-2 specific Monitor Channel Data Structure see appendix, page 64).
Figure 7 Table 5 TSS1 = 0, TSS0 = 0 IOM(R)-2 - SICOFI(R)-2 TS Channels 1 2
Semiconductor Group
TSS1 = 0, TSS0 = 1
TSS1 = 1, TSS0 = 0
TSS1 = 1, TSS0 = 1 Voice Channel
Voice TS Channel
Voice TS Channel
Voice TS Channel
TS0 A TS0 B
TS2 A TS2 B
17
TS4 A TS4 B
TS6 A TS6 B
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3 Programming the IOM(R)-2 - SICOFI(R)-2
With the appropriate commands, the IOM-2 - SICOFI-2 can be programmed and verified very flexibly via the IOM-2 Interface monitor channel. Data transfer to the IOM-2 - SICOFI-2 starts with a SICOFI-specific address byte (81H). With the second byte one of 3 different types of commands (SOP, XOP and COP) is selected. Each of those can be used as a write or read command. Due to the extended IOM-2 - SICOFI-2 feature control facilities, SOP, COP and XOP commands contain additional information (e.g. number of subsequent bytes) for programming (write) and verifying (read) the IOM-2 - SICOFI-2 status. A write command is followed by up to 8 bytes of data. The IOM-2 - SICOFI-2 responds to a read command with its IOM-2 specific address and the requested information, that is up to 8 bytes of data (see programming Procedure, page 18). Attention: Each byte on the monitor channel, has to be sent twice at least, according to the IOM-2 Monitor handshake procedure (For more information on IOM-2 specific Monitor Channel Data Structure see appendix, page 64). 3.1 Types of Monitor Bytes
The 8-bit Monitor Bytes have to be interpreted as either commands or status information stored in Configuration Registers or the Coefficient RAM. There are three different types of IOM-2 - SICOFI-2 commands which are selected by bit 3 and 4 as shown below. SOP STATUS OPERATION: IOM-2 - SICOFI-2 status setting/monitoring 4 1 XOP Bit EXTENDED OPERATIO: 7 X COP Bit COEFFICIENT OPERATION: 7 6 5 4 0 6 5 4 1 3 0 C/I channel configuration/evaluation 3 1 filter coefficient setting/monitoring 3 2 1 0 2 1 0 2 1 0
Bit
7
6
5
Semiconductor Group
18
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Programming the IOM(R)-2 - SICOFI(R)-2 Storage of Programming Information: 4 configuration registers per channel: CR1, CR2, CR3, CR4 accessed by SOP commands 4 common configuration registers: XR1, XR2, XR3 and XR4 accessed by XOP commands (the contents are valid for two voice channels i.e. 1 IOM-2 time slot) CRAM accessed by COP commands
1 coefficient RAM per channel: 3.2 3.2.1 DD Address SOP-Write 1 Byte CR1
IOM(R)-2 - SICOFI(R)-2 Commands SOP - Write Commands 7 6 5 4 3 2 1 0 Bit 10000001 0 10001 Data 76543210 Idle Idle Idle DU
DD Address SOP-Write 2 Bytes CR2 CR1
7 6 5 4 3 2 1 0 Bit 10000001 0 10010 Data Data
76543210 Idle Idle Idle Idle 0
DU
DD Address SOP-Write 3 Bytes CR3 CR2 CR1
7 6 5 4 3 2 1 0 Bit 10000001 0 10011 Data Data Data
76543210 Idle Idle Idle Idle Idle
DU
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2
DD Address SOP-Write 4 Bytes CR4 CR3 CR2 CR1 3.2.2 DD Address XOP-Write 2 Bytes XR2 XR1
7 6 5 4 3 2 1 0 Bit 10000001 0 10100 Data Data Data Data
7 6 5 4 3 2 1 0 DU Idle Idle Idle Idle Idle Idle
XOP - Write Commands 7 6 5 4 3 2 1 0 Bit 10000001 0 11010 Data Data 76543210 Idle Idle Idle Idle DU
DD Address XOP-Write 3 Bytes XR3 XR2 XR1
7 6 5 4 3 2 1 0 Bit 10000001 0 11010 Data Data Data
76543210 Idle Idle Idle Idle Idle
DU
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.2.3 DD Address COP-Write 4 Bytes Coeff. 4 Coeff. 3 Coeff. 2 Coeff. 1 COP - Write Commands 7 6 5 4 3 2 1 0 Bit 10000001 0 01 Data Data Data Data 76543210 Idle Idle Idle Idle Idle Idle DU
DD Address COP-Write 8 Bytes Coeff. 8 Coeff. 7 Coeff. 6 Coeff. 5 Coeff. 4 Coeff. 3 Coeff. 2 Coeff. 1
7 6 5 4 3 2 1 0 Bit 10000001 0 00 Data Data Data Data Data Data Data Data
76543210 Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle
DU
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.2.4 DD Address SOP-Read 1 Byte SOP - Read Commands 7 6 5 4 3 2 1 0 Bit 10000001 1 10001 Idle Idle 76543210 Idle Idle 1 0 0 0 0 0 0 1 Address Data CR1 DU
DD Address SOP-Read 2 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 10010 Idle Idle Idle
76543210 Idle Idle
DU
1 0 0 0 0 0 0 1 Address Data Data CR2 CR1
DD Address SOP-Read 3 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 10011 Idle Idle Idle Idle
76543210 Idle Idle
DU
1 0 0 0 0 0 0 1 Address Data Data Data CR3 CR2 CR1
DD Address SOP-Read 4 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 10100 Idle Idle Idle Idle Idle
76543210 Idle Idle
DU
1 0 0 0 0 0 0 1 Address Data Data Data Data CR4 CR3 CR2 CR1
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.2.5 DD Address XOP-Read 1 Byte XOP - Read Commands 7 6 5 4 3 2 1 0 Bit 10000001 1 11001 Idle Idle 76543210 Idle Idle 1 0 0 0 0 0 0 1 Address Data XR1 DU
DD Address XOP-Read 2 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 11010 Idle Idle Idle
7 6 5 4 3 2 1 0 DU Idle Idle 1 0 0 0 0 0 0 1 Address Data Data XR2 XR1
DD Address XOP-Read 3 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 11011 Idle Idle Idle Idle
76543210 Idle Idle
DU
1 0 0 0 0 0 0 1 Address Data Data Data XR3 XR2 XR1
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.2.6 DD Address COP-Read 4 bytes COP - Read Commands 7 6 5 4 3 2 1 0 Bit 10000001 1 01 Idle Idle Idle Idle Idle 76543210 Idle Idle 1 0 0 0 0 0 0 1 Address Data Data Data Data Coeff.4 Coeff.3 Coeff.2 Coeff.1 DU
DD Address COP-Read 8 Bytes
7 6 5 4 3 2 1 0 Bit 10000001 1 00 Idle Idle Idle Idle Idle Idle Idle Idle Idle
76543210 Idle Idle 1 0 0 0 0 0 0 1 Address Data Data Data Data Data Data Data Data
DU
Coeff.8 Coeff.7 Coeff.6 Coeff.5 Coeff.4 Coeff.3 Coeff.2 Coeff.1
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.2.7 DD Address SOP-Write 4 Bytes CR4 CR3 CR2 CR1 XOP-Write 2 Bytes XR2 XR1 COP-Write 4 Bytes Coeff. 4 Coeff. 3 Coeff. 2 Coeff. 1 SOP-Read 3 Bytes 1 0 0 Example for a Mixed Command 7 6 5 4 3 2 1 0 Bit 10000001 0 10100 Data Data Data Data 11010 Data Data 01 Data Data Data Data 10011 Idle Idle Idle Idle Address COP-Read 4 Bytes 10000001 1 01 Idle Idle Idle Idle Idle Address XOP-Read 1 Byte 10000001 1 11001 Idle Idle
Semiconductor Group 25
76543210 Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle Idle 1 0 0 0 0 0 0 1 Address Data Data Data Idle Idle 1 0 0 0 0 0 0 1 Address Data Data Data Data Idle Idle 1 0 0 0 0 0 0 1 Address Data XR1 CR3 CR2 CR1
DU
Coeff.4 Coeff.3 Coeff.2 Coeff.1
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.3 SOP Command
To modify or evaluate the IOM-2 - SICOFI-2IOM-2 - SICOFI-2 status, the contents of up to four configuration registers CR1, CR2, CR3 and CR4 may be transferred to or from the IOM-2 - SICOFI-2. This is started by a SOP-Command (status operation command). Bit 7 AD AD 6 RW 5 PWRUP 4 1 3 0 2 LSEL2 1 LSEL1 0 LSEL0
Address Information AD = 0 IOM-2 - SICOFI-2 channel 1 is addressed with this cmd. AD = 1 IOM-2 - SICOFI-2 channel 2 is addressed with this cmd. Read/Write Information: Enables reading from the IOM-2 - SICOFI-2 or writing information to the IOM-2 - SICOFI-2 RW = 0 Write to IOM-2 - SICOFI-2 RW = 1 Read from IOM-2 - SICOFI-2 Power Up / Power Down PWRUP = 1 sets the assigned channel (see bit AD) of IOM-2 - SICOFI-2 to power-up (operating mode) PWRUP = 0 resets the assigned channel of IOM-2 - SICOFI-2 to power-down (standby mode) Length select information (see also programming procedure) This field identifies the number of subsequent data bytes LSEL = 000 0 bytes of data are following LSEL = 001 1 byte of data is following (CR1) LSEL = 010 2 bytes of data are following (CR2, CR1) LSEL = 011 3 bytes of data are following (CR3, CR2, CR1) LSEL = 100 4 bytes of data are following (CR4, CR3, CR2, CR1)
RW
PWRUP
LSEL
All other codes are reserved for future use! It is possible to program each configuration register separately, just by putting only one byte into the FIFO of the upstream master device (e.g. EPIC), and aborting after transmission of one (or n) byte.
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.3.1 CR1 Configuration Register 1
Configuration register CR1 defines the basic IOM-2 - SICOFI-2 settings, which are: enabling/disabling the programmable digital filters and tone generators. Bit 7 TH TH 6 IM/R1 5 FRX 4 FRR 3 AX 2 AR 1 ETG2 0 ETG1
Enable TH- (Trans Hybrid Balancing) Filter TH = 0: TH = 1: TH-filter disabled TH-filter enabled IM-filter and R1-filter disabled IM-filter and R1-filter enabled FRX-filter disabled FRX-filter enabled FRR-filter disabled FRR-filter enabled AX-filter disabled AX-filter enabled AR-filter disabled AR-filter enabled programmable tone generator 2 is disabled programmable tone generator 2 is enabled programmable tone generator 1 is disabled programmable tone generator 1 is enabled
IM/R1
Enable IM-(Impedance Matching) Filter and R1-Filter IM/R1 = 0: IM/R1 = 1:
FRX
Enable FRX (Frequency Response Transmit)-Filter FRX = 0: FRX = 1:
FRR
Enable FRR (Frequency Response Receive)-Filter FRR = 0: FRR = 1:
AX
Enable AX-(Amplification/Attenuation Transmit) Filter AX = 0: AX = 1:
AR
Enable AR-(Amplification/Attenuation Receive) Filter AR = 0: AR = 1:
ETG2
Enable programmable tone generator 21) ETG2 = 0: ETG2 = 1:
ETG1
Enable programmable tone generator 1 ETG1 = 0: ETG1 = 1:
1)
Tone generator 2 is not available if Level Metering Function is enabled!
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.3.2 Bit 7 TH-Sel TH-Sel CR2 Configuration Register 2 6 5 LM 4 LMR 3 LAW 2 LIN 1 PTG2 0 PTG1
2 bit field to select one of two programmed TH-filter coefficient sets TH-Sel = 0 0: TH-filter coefficient set 1 is selected TH-Sel = 0 1: TH-filter coefficient set 2 is selected
LM
Level Metering function1) LM = 0: LM = 1: level metering function is disabled level metering function is enabled level detected was lower than the reference level detected was higher than the reference A-Law is selected -Law (255 PCM) is selected PCM-mode is selected linear mode is selected2) fixed frequency for tone generator 2 is selected (1 kHz) programmed frequency for tone generator 2 is selected fixed frequency for tone generator 1 is selected (1 kHz) programmed frequency for tone generator 1 is selected
LMR
Result of Level Metering function (this bit can not be written) LMR = 0: LMR = 1:
LAW
PCM - law selection LAW = 0: LAW = 1:
LIN
Linear mode selection LIN = 0: LIN = 1:
PTG2
User programmed frequency or fixed frequency is selected PTG2 = 0: PTG2 = 1:
PTG1
User programmed frequency or fixed frequency is selected PTG1 = 0: PTG1 = 1:
1)
2)
Explanation of the level metering function: A signal fed to A/-Law compression via AX- and HPX-filters (from a digital loop, or externally via VIN), is rectified, and the power is measured. If the power exceeds a certain value, loaded to XR4, bit LMR is set to `1'. The power of the incoming signal can be adjusted by AX-filters. During Linear operation only one 16 bit voice channel, is available per time slot. Depending on the address bit (AD) the voice-data of channel 1 or 2 is transmitted. The other voice channel is not available during this time.
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.3.3 Bit 7 CR3 Configuration Register 3 6 COT/R COT/R 5 4 0 3 IDR 2 1 Version 0
Selection of Cut Off Transmit/Receive Paths 0 0 0: 0 0 1: 0 1 0: Normal Operation COT_16K COT_PCM Cut Off Transmit Path at 16 kHz (input of TH-Filter) Cut Off Transmit Path at 8 kHz (input of compression) (output is zero for -law and linear mode, 1 LSB for A-law) Cut Off Receive Path at 4 MHz (POFI-output) Cut Off Receive Path at 64 kHz (IM-filter input)
1 0 1: 1 1 0: IDR
COR_PFI COR_64K
Initialize Data RAM IDR = 0: IDR = 1: Normal operation is selected Contents of Data RAM is set to 0 (used for production test purposes)
Version
The Version number shows the actual design version of IOM-2-SICOFI-2 (100 for PEB 2265 V1.1)
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2
Figure 8 CUT OFF`s' and Loops
Semiconductor Group
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1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.3.4 Bit 7 CR4 Configuration Register 4 6 5 4 3 AGX 2 AGR 1 D-HPX 0 D-HPR
Test-Loops Test-Loops
4 bit field for selection of Analog and Digital Loop Backs 0 0 0 0: 0 0 0 1: 0 0 1 1: 0 1 0 0: 0 1 0 1: 1 0 0 0: 1 0 0 1: 1 1 0 0: 1 1 0 1: 1 1 1 1: ALB-PFI ALB-4M ALB-8K no loop back is selected (normal operation) analog loop back via PREFI-POFI is selected analog loop back via 4 MHz is selected analog loop back via 8 kHz (linear) is selected digital loop back via 4 MHz is selected digital loop back via 64 kHz is selected
ALB-PCM analog loop back via 8 kHz (PCM) is selected
DLB-ANA digital loop back via analog port is selected DLB-4M DLB-64K DLB-128K digital loop back via 128 kHz is selected DLB-PCM digital loop back via PCM-registers is selected analog gain is disabled analog gain is enabled (6,02dB amplification) analog gain is disabled analog gain is enabled (6,02dB attenuation)
AGX
Analog gain in transmit direction AGX = 0: AGX = 1:
AGR
Analog gain in receive direction AGR = 0: AGR = 1:
D-HPX
Disable highpass in transmit direction D-HPX = 0: transmit high pass is enabled D-HPX = 1: transmit high pass is disabled 1)
D-HPR
Disable highpass in receive direction D-HPR = 0: receive high pass is enabled D-HPR = 1: receive high pass is disabled 2)
1) 2)
In this case the transmit-path signal is attenuated 0.06 dB In this case the receive-path signal is attenuated 0.12 dB
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.4 COP Command
With a COP Command coefficients for the programmable filters can be written to the IOM-2 - SICOFI-2 Coefficient RAM or read from the Coefficient RAM via the IOM-2 interface for verification Bit 7 AD AD 6 RW Address AD = 0 AD = 1 5 RST 4 0 3 CODE3 2 CODE2 1 CODE1 0 CODE0
IOM-2 - SICOFI-2 channel 1 is addressed IOM-2 - SICOFI-2 channel 2 is addressed
RW
Read/Write RW = 0 Subsequent data is written to the IOM-2 - SICOFI-2 RW = 1 Read data from IOM-2 - SICOFI-2 Reset RST = 1 Reset IOM-2 - SICOFI-2 (same as RESET-Pin, valid for all two channels) includes number of following bytes and filter-address 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 TH-Filter coefficients (part 1) 1 TH-Filter coefficients (part 2) 0 TH-Filter coefficients (part3) 0 IM-Filter coefficients (part1) 1 IM-Filter coefficients (part2) 0 FRX-Filter coefficients 1 FRR-Filter coefficients 0 AX-Filter coefficients 1 AR-Filter coefficients 0 TG1-Filter coefficients 1 TG2-Filter coefficients (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 8 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data) (followed by 4 bytes of data)
RST
CODE
Semiconductor Group
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1997-07-01
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Programming the IOM(R)-2 - SICOFI(R)-2 How to Program the Filter Coefficients TH-Filter: Two sets of TH-filter coefficients can be loaded to the IOM-2 - SICOFI-2.Each of the two sets can be selected for any of the two IOM-2 - SICOFI-2 channels, by setting the value of TH-SEL in configuration register CR2. Coefficient set 1 is loaded to the IOM-2-SICOFI-2 via channel 1, set 2 is loaded via channel 2.
AX, AR, IM, FRX, FRR-Filter: An individual coefficient set is available for each of the two channels Tone-Generators: An individual coefficient set is available for each of the two channels An independent set of coefficients is available for all the two channels, for all the filters and Tone-Generators. Two sets of TH-filter coefficients can be loaded to the IOM-2 - SICOFI-2. Each of the two sets can be selected for any of the two IOM-2 - SICOFI-2 channels, by setting the value of TH-SEL in configuration register CR2. Coefficients set #1 is loaded to the IOM-2-SICOFI-2 via channel 1, set #2 is loaded via channel 2 and so on.
Note: After RESET coefficient set #1 is used for all of the two channels, as all bits in configuration register CR2 are set to `0'.
PEB 2265, IOM2-SICOFI(R) 2
channel 1 IM part1 Filter IM part2 Filter FRX-Filter FRR-Filter AX-Filter AR-Filter TG1, TG2
general registers
chan. 1 chan. 2 TH part1 TH part1 TH part2 TH part2
channel 2 IM part1 Filter IM part2 Filter FRX-Filter FRR-Filter AX-Filter AR-Filter TG1, TG2
channel registers
Figure 9
Semiconductor Group
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1997-07-01
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Programming the IOM(R)-2 - SICOFI(R)-2 3.5 XOP Command
With the XOP command, the IOM-2 - SICOFI-2 C/I channel in the selected time slot1) is configured and evaluated. Bit 7 0 RW 6 RW 5 0 4 1 3 1 2 LSEL2 1 LSEL1 0 LSEL0
Read / Write Information: Enables reading from the IOM-2 - SICOFI-2 or writing information to the IOM-2 - SICOFI-2 RW = 0 Write to IOM-2 - SICOFI-2 RW = 1 Read from IOM-2 - SICOFI-2 Length select information, for setting the number of subsequent data bytes LSEL = 000 0 bytes of data are following LSEL = 001 1 byte of data is following (XR1) LSEL = 010 2 bytes of data are following (XR2, XR1) LSEL = 011 3 bytes of data are following (XR3, XR2, XR1) LSEL = 100 4 bytes of data are following (XR4, XR3, XR2, XR1) XR1 Extended Register2) 7 SB2_1 6 SB2_0 5 4 SI2_01) 3 SB1_1 2 SB1_0 1 SI1_01) 0 SI1_01)
LSEL
3.5.1 Bit
1)
SI2_01)
Bits SI1_0 and SI2_0 have special meaning depending on contents of XR2 (see page 35).
SB2_1 SB2_0 SI2_0 SB1_1 SB1_0 SI1_0
status of pin SB2_1 is transferred to the upstream master device status of pin SB2_0 is transferred to the upstream master device status of pin SI2_0 is transferred to the upstream master device status of pin SB1_1 is transferred to the upstream master device status of pin SB1_0 is transferred to the upstream master device status of pin SI1 _0 is transferred to the upstream master device
1) 2)
IOM-2 time slot TS0, TS2, TS4 or TS6, by pin-strapping the pins TSS0 and TSS1 Register XR1 can only be read.
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.5.2 XR2 Extended Register 2
Register XR2 configures the data-upstream command/indication channel. Bit 7 6 N Upstream Update Interval N To restrict the rate of upstream C/I-bit changes, deglitching (persistence checking) of the status information from the SLIC may be applied. New status information will be transmitted upstream, after it has been stable for N milliseconds. N is programmable in the range of 1 to 15 ms in steps of 1 ms, with N = 0 the deglitching is disabled. Field N 0 0 0 . . 1 1 0 0 0 . . 1 1 0 0 1 . . 1 1 0 1 0 . . 0 1 Update Interval Time Deglitching is disabled Upstream transmission after 1 ms Upstream transmission after 2 ms . . Upstream transmission after 14 ms Upstream transmission after 15 ms 5 4 3 2 T 1 0
Detector Select Sampling Interval T SLICs with multiplexed loop- and ground-key-status, which have a single status output pin for carrying the loop- and ground-keystatus information, need a special detector select input. Field T 0 0 0 . . 1 1 0 0 0 . . 1 1 0 0 1 . . 1 1 0 1 0 . . 0 1 Time Interval T between Detector selected High States Detector select output LGKM0 is program. To 0 permanently Time interval T is 1 ms Time interval T is 2 ms . . Time interval T is 14 ms Detector select output LGKM0 is program. to 1 permanently
LGKM0 is detector select output for channel 1 and 2.
Semiconductor Group 35 1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 SLICs with Multiplexed Loop / Ground Key Detect
IOM2-SICOFI-2 (channel 1 and 2)
XR1
0 1 2 3
SLIC detector select control T
SI1_0 SB1_0 SB1_1
Loop/GND Key input from SLIC
SLIC #1
LGKM0
Data Upstream
programmable T
4 5 6 7
SI2_0 SB2_0 SB2_1
Loop/GND Key input from SLIC
SLIC #2
Figure 10 IOM-2 - SICOFI-2 pin LGKM0 is a detector select output. This command output pin are normally set to logical `0', such that the SLIC outputs loop status, which is passed to XR1-bits 0 and 4 via indication pins SI1_0 and SI2_0. Every T milliseconds, the detector select output change to logical `1' for a time of 125 s (period FSC). During this time the ground key status is read from the SLIC and transferred upstream using XR1 - bits 1 and 5 via indication pins SIx_0 and SIy_0. The time interval T is programmable from 1 ms to 14 ms in 1ms steps. It is possible to program the output to be permanently logical `0' or `1'.
Semiconductor Group
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Programming the IOM(R)-2 - SICOFI(R)-2 3.5.3 XR3 Extended Register 3
This register controls the direction of the programmable C/I pins. Bit 7 6 5 0 4 0 3 2 1 0 0 0
PSB2_1 PSB2_0 PSB2_1
PSB1_1 PSB1_0
Programmable bi-directional C/I pin SB2_1 is programmed PSB2_1 = 0: pin SB2_1 is indication input PSB2_1 = 1: pin SB2_1 is command output Programmable bi-directional C/I pin SB2_0 is programmed PSB2_0 = 0: pin SB2_0 is indication input PSB2_0 = 1: pin SB2_0 is command output Programmable bi-directional C/I pin SB1_1 is programmed PSB1_1 = 0: pin SB1_1 is indication input PSB1_1 = 1: pin SB1_1 is command output Programmable bi-directional C/I pin SB1_0 is programmed PSB1_0 = 0: pin SB1_0 is indication input PSB1_0 = 1: pin SB1_0 is command output XR4 Extended Register 4
PSB2_0
PSB1_1
PSB1_0
3.5.4
This register holds the offset value for the level metering function. It is only available via the first used time slot. Bit 7 OF7 3.6 6 OF6 5 OF5 4 OF4 3 OF3 2 OF2 1 OF1 0 OF0
SLIC Interface
The signaling connection between IOM-2 - SICOFI-2 and a SLIC is performed by the IOM-2 - SICOFI-2 command/indication pins. Data received from the downstream C/I byte are inverted and transferred to command output pins (SB, SO). Data on input pins (SI, SB) are inverted and transferred to the upstream C/I-byte.
Semiconductor Group
37
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PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.7 IOM(R)-2 Interface Command/Indication Byte
The IOM-2 - SICOFI-2 offers a 8 pin parallel command/indication SLIC interface per channel. Indication Input Pins Command Output Pins Program. Command/Indication Pins SIx_0, SIx_1 SIx_2 SOx_0, SOx_1, SOx_2 SBx_0, SBx_1 (with x: 1 ... 4)
Data present at SIx_0, SIx_1, SIx_2 and SBx_0, SBx_1 (if programmed as input) are sampled, inverted and transferred upstream. Data received downstream from IOM-2-interface are latched, inverted and fed to SOx_0, SOx_1, SOx_2 and SBx_0, SBx_1 (if output). Data-Downstream C/I Channel Byte Format (receive) The IOM-2 channel contains 6 bits (for two voice channels) in both directions for analog devices like the IOM-2 - SICOFI-2. As the IOM-2 - SICOFI-2 has up to five command output pins per channel (depending on XR3) it is not possible to send commands to all pins at a time. So C/I-channel bit 5 is used as an address bit to select the channel for the command data on C/I-channel bits 4 ... 0. General Case: Bit 5 AD 4 SBx_1 3 SBx_0 2 SOx_2 1 SOx_1 0 SOx_0
Example for IOM-2 - SICOFI-2 channels 1 and 2 (IOM-2 time slot 0): Bit
1)
5 1
4 SB1_11)
3 SB1_01)
2 SO1_2
1 SO1_1
0 SO1_0
If SBx_y is programmed as command output.
Bit
5 0
4 SB2_11)
3 SB2_01)
2 SO2_2
1 SO2_1
0 SO2_0
Semiconductor Group
38
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 Data Upstream C/I Channel Byte Format (transmit) As the C/I-channel holds only 6 bits for two voice channels and the IOM-2 - SICOFI-2 has up to five indication pins per voice channel, only pins SI1_1 and SI1_2 for voice channel 1, and pins SI2_1 and SI2_2 for voice channel 2 are fed directly to the C/I-channel. Any change at one of the other indication pins (SIx_0, SBx_0 and SBx_1) will generate an interrupt per channel, which is transmitted upstream immediately (C/I-channel bits 2 and 5). Data on those pins is fed to register XR1 and can be evaluated with a XOP-read command.
IOM -2 - SICOFI -2 (2 Channels, 1 Time-Slot) SB2_1 SB2_0 SI2_0 SI2_2 SI2_1 SB1_1 SB1_0 SI1_0 SI1_2 SI1_1
R
R
hange
"0" on C
C/I5 INT2
C/I4 SI2_2
C/I3 SI2_1
"0" on C
hange
"0" on C
"0" on C
XR1(7) SB2_1
If an interrupt occurs in one channel, changes in the neighboring channel will also generate an interrupt.
ITD09991
"0" on Ch ang e
"0" on Ch
XR1(6) SB2_0
hange
hange
ang e
XR1(3) SB1_1
C/I2 INT1
C/I1 SI1_2
C/I0 SI1_1
XR1(5,4) SI2_0
XR1(2) SB1_0
XR1(1,0) SI1_0
Channel 2
Channel 1
Figure 11
Semiconductor Group
39
1997-07-01
Figure 12 Data Flow
Deglitching Time Sampling of Pins (value between is ignored)
Semiconductor Group
2 1 2 Pin Transferred Directly Via C/I Data on C/I-Channel 2 Change 2 1 2 Pin Transferred Via Register Interrupt Transferred on C/I DD Read-Register Signal Data Transferred in Register
1
40
Change 1 1
Programming the IOM(R)-2 - SICOFI(R)-2
Data on Signaling Pins has to be stable for at least 2 samples, to be transferred DU or to trigger an interrupt. During active interrupt data on pins transferred via Register is not sampled. After clearing the interrupt, change 2 is detected, which generates a new interrupt.
PEB 2265
1997-07-01
ITD09992
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.8 Operating Modes
Figure 13 3.8.1 RESET (Basic setting mode)
Upon initial application of VDD or resetting pin RESET to `1' during operation, or by software-reset (see COP command), the IOM-2 - SICOFI-2 enters a basic setting mode. Basic setting means, that the IOM-2 - SICOFI-2 configuration registers CR1q ... CR4 and XR1 ... XR3 are initialized to `0' for all channels. All programmable filters are disabled, A-law is chosen, all programmable command/indication pins are inputs. The two tone generators as well as any testmodes are disabled. There is no persistence checking. Receive signaling registers are cleared. DU-pin is in high impedance state, the analog outputs and the signaling outputs are forced to ground.
Semiconductor Group
41
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 Table 6 CR1 ... CR4 XR1 ... XR4 Coefficient RAM Command Stack DD-input DU-output VOUT1,2 SBx_y SOx_y 00H 00H Not defined Cleared Ignored High impedance GNDA1,2 Input GNDD
If any voltage is applied to any input-pin before initial application of VDD, the IOM-2 - SICOFI-2 may not enter the basic setting mode. In this case it is necessary to reset the IOM-2 - SICOFI-2 or to initialize the IOM-2 - SICOFI-2 configuration registers to `0'. The IOM-2 - SICOFI-2 leaves this mode automatically with the beginning of the next 8-kHz frame (RESET-pin is released). 3.8.2 Standby Mode
After releasing the RESET-pin, (RESET-state), beginning with the next 8 kHz frame, the IOM-2 - SICOFI-2 will enter the Standby mode. The IOM-2 - SICOFI-2 is forced to standby mode with the PWRUP bit set to `0' in the SOP command (POWERDOWN). The two channels must be programmed separately. During standby mode the serial IOM-2 - SICOFI-2 IOM-2 interface is ready to receive and transmit commands and data. Received voice data on DD-pin will be ignored. IOM-2 - SICOFI-2 configuration registers and coefficient RAM can be loaded and read back in this mode. Data downstream C/I-channel data is fed to appropriate command pins. Data on indication pins is transmitted data upstream. Table 7 IOM-2 Voice Channels VOUT1, 2 3.8.3 Operating Mode `11111111' (idle) GNDA1, 2
The operating mode for any of the two channels is entered upon recognition of a PWRUP bit set to `1' in a SOP command for the specific channel.
Semiconductor Group
42
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.9 Programmable Filters
Based on an advanced digital filter concept, the PEB 2265 provides excellent transmission performance and high flexibility. The new filter concept leads to a maximum independence between the different filter blocks. 3.9.1 Impedance Matching Filter
* Realization by 3 different loops - 4 MHz: Multiplication by a constant (12 bit) - 128 kHz: Wave Digital Filter (IIR) (60 bit) improves low frequency response) - 64 kHz: FIR-Filter (48 bit) (for fine-tuning) * Improved stability behavior of feedback loops * Real part of termination impedance positive under all conditions * Improved overflow performance for transients * Return loss better 30 dB 3.9.2 Transhybrid Balancing (TH) Filter
* New concept: 2 loops at 16 kHz * Flexible realization allows optimization of wide impedance range * Consists of a fixed and a programmable part - 2nd order Wave Digital Filter (IIR) (106 bit) (improves low frequency response) - 7-TAP FIR-Filter (84 bit) (for fine-tuning) * Trans-Hybrid-Loss better 30 dB (typically better 40 dB, device only) * Adaptation to different lines by: - Easy selection between two different downloaded coefficient sets 3.9.3 Filters for Frequency Response Correction
* For line equalization and compensation of attenuation distortion * Improvement of Group-Delay-Distortion by using minimum phase filters (instead of linear phase filters) * FRR filter for correction of receive path distortion - 5 TAP programmable FIR filter operating at 8 kHz (60 bit) * FRX filter for correction of transmit path distortion - 5 TAP programmable FIR filter operating at 8 kHz (60 bit) * Frequency response better 0.1 dB
Semiconductor Group
43
1997-07-01
PEB 2265
Programming the IOM(R)-2 - SICOFI(R)-2 3.9.4 Amplification/Attenuation -Filters AX1, AX2, AR1, AR2
* Improved level adjustment for transmit and receive * Two separate filters at each direction for - Improved trans-hybrid balancing - Optimal adjustment of digital dynamic range - Gain adjustments independent of TH-filter 3.9.5 Amplification/Attenuation Receive (AR1, AR2)-Filter range 3 ... - 14 dB: step size 0.02 ... 0.05 dB range - 14 ... - 24 dB:step size 0.5 dB
Step size for AR-Filter
3.9.6
Amplification/Attenuation Transmit (AX1, AX2)-Filter range - 3 ... 14 dB: step size 0.02 ... 0.05 dB range 14 ... 24 dB: step size 0.5 dB
Step size for AX-Filter
Semiconductor Group
44
1997-07-01
PEB 2265
QSICOS Software 4 QSICOS Software
The QSICOS-software has been developed to help to obtain an optimized set of coefficients both quickly and easily. The QSICOS program runs on any PC with at least 575 Kbytes of memory. This also requires MS-DOS Version 5.0 or higher, as well as extended memory.
Calculation-Controlfile
RD/dB
Country-Spec
Simulation (PSPICE)
Automatic K-Param Extraction
Line Interface
K11=(Zin-Zg)/(Zin+Zg)
f/Hz
Line Interface
K12=2*V1/V3
QSICOS
K-Parameter InterfaceFile
Line Interface
K21=V2/Vg
Line Interface
K22=V2/V3
Software for Filter-Coefficients-Optimization
SICOFI Coefficients File
Figure 14 4.1 QSICOS Supports
* Calculation of coefficients for the - Impedance Filter (IM) for return loss calculation - FRR and FRX-Filters for frequency response in receive and transmit path - AR1, AR2 and AX1, AX2-Filter for level adjustment in receive and transmit path - Trans-Hybrid Balancing Filter (TH) and - two programmable tone generators (TG 1 and TG 2) * Simulation of the PEB 2265 and SLIC system with fixed filter coefficients allows simulations of tolerances which may be caused e.g. by discrete external components. * Graphical output of transfer functions to the screen for - Return Loss - Frequency responses in receive and transmit path - Transhybrid Loss * Calculation of the PEB 2265 and SLIC system stability. The IM-Filter of the PEB 2265 adjust the total system impedance by making a feedback loop. Because the line is also a part of the total system, a very robust method has to used to avoid oscillations and to ensure system stability. The input impedance of the PEB 2265 and SLIC combination is calculated. If the real part of the system input impedance is positive, the total system stability can be guaranteed.
Semiconductor Group
45
1997-07-01
PEB 2265
Transmission Characteristics 5 Transmission Characteristics
The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) needs a complete knowledge of the IOM-2 - SICOFI-2's analog environment, and it is suggested to use the QSICOS-program for calculating the propriate coefficients. Unless otherwise stated, the transmission characteristics are guaranteed within the test conditions. Test Conditions
TA = 0 C to 70 C; VDD = 5 V 5 %; GNDA1 ... 4 = GNDD = 0 V RL1)) > 20 k; CL < 20 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1;
HPR and HPX enabled; AR2) = AR1 + AR2 = AX3) = AX1 + AX2 = 0 to - 13 dB for sine-wave-, and 0 to - 11 dB for CCITT-noise-measurements 0 to 13 dB for sine-wave-, and 0 to 11 dB for CCITT-noise-measurements
f = 1014 Hz; 0 dBm0; A-Law or -Law; AGX = 0 dB, 6.02 dB, AGR = 0 dB, - 6.02 dB; In Transmit direction for -law an additional gain of 1.94 dB is implemented automatically, in the companding block (CMP). This additional gain has to be considered at all gain calculations, and reduces possible AX-gain. A 0dBm044)) signal is equivalent to 1.095 [1.0906] Vrms. A +3.14 [3.17] dBm0 signal is equivalent to 1.57 Vrms which corresponds to the overload point of 2.223 V (A-law,[-law]). When the gain in the receive path is set at 0 dB, an 1014 Hz PCM sinewave input with a level 0dBm0 will correspond to a voltage of 1.095 Vrms at A-Law (1,0906 V -Law) at the analog output. When the gain in the transmit path is set at 0 dB, an 1014Hz sine wave signal with a voltage of 1.095 Vrms A-Law (1.0906 V -Law) will correspond to a level of 0 dBm0 at the PCM output.
1) 2)
3)
4)
RL,Cl forms the load on VOUT Consider, in a complete System, AR = AR1 + AR2 + FRR + R1 = 0 to - 13 dB (- 11 dB for CCITT-noise-measurement) Consider, in a complete System, AX = AX1 + AX2 + FRX = 0 to 13 dB (11 dB for CCITT-noise-measurement) for A-Law, 0 to 11 dB (9 dB for CCITT-noise-measurement) for -Law The absolute power level in decibels referred to the PCM interface levels.
Semiconductor Group
46
1997-07-01
PEB 2265
Transmission Characteristics Table 8 Parameter Gain absolute (AGX = AGR = 0) TA = 25 C; VDD = 5 V TA = 0 - 70 C; VDD = 5 V 5 % Gain absolute (AGX = 6.02 dB, AGR = - 6.02 dB) TA = 25 C; VDD = 5 V TA = 0 - 70 C; VDD = 5 V 5 % Harmonic distortion, 0 dBm0; f = 1000 Hz; 2nd, 3rd order Intermodulation1) R2 R3 HD IMD IMD CT Symbol min G - 0.15 0.10 + 0.15 - 0.25 + 0.25 dB dB Limit Values typ. max. Unit
- 0.15 0.10 + 0.15 - 0.25 + 0.25 - 50 - 46 - 56 - 85 - 80 - 44
dB dB dB dB dB dB
Crosstalk 0 dBm0; f = 200 Hz to 3400 Hz any combination of direction and channel Idle channel noise, Transmit, A-law, psophometric VIN = 0 V Transmit, -law, C-message VIN = 0 V Receive, A-law, psophometric idle code + 0 Receive, -law, C-message idle code + 0
1)
NTP NTC NRP NRC
- 85 5
- 67.4 17.5 - 78.0 12.0
dBm0p dBmc dBm0p dBmc
Using equal-level, 4-tone method (EIA) at a composite level of - 13 dBm0 with frequencies in the range between 300 Hz and 3400 Hz.
Semiconductor Group
47
1997-07-01
PEB 2265
Transmission Characteristics 5.1 5.1.1 Frequency Response Receive: reference frequency 1 kHz, input signal level 0 dBm0
2 dB
ITD10002
Attenuation
1 0.65 dB 0 0.125 dB -0.125 dB
HPR is Off
-1 0 0.2 0.3
1
2
kHz 3 3.2 3.4
f
Figure 15 5.1.2 Transmit: reference frequency 1 kHz, input signal level 0 dBm0
2 dB
ITD10001
Attenuation
1 0.65 dB 0 0.125 dB -0.125 dB
-1
0 0.2 0.1 0.3
1
2
kHz 3 3.2 3.4
f
Figure 16
Semiconductor Group
48
1997-07-01
PEB 2265
Transmission Characteristics 5.2 Group Delay
Maximum delays when the IOM-2 - SICOFI-2 is operating with H(TH) = H(IM) = 0 and H(FRR) = H(FRX) = 1 including delay through A/D- and D/A converters. Specific filter programming may cause additional group delays. Group Delay deviations stay within the limits in the figures below. 5.2.1 Table 9 Parameter Transmit delay Receive delay 5.2.2 Symbol min. DXA DRA Limit Values typ. max. 300 250 s s Unit Reference Group Delay absolute values: Input signal level 0 dBm0
Group Delay Distortion transmit: Input signal level 0 dBm0
500 s tG 400 300 200 150 100 0
ITD09999
85 0.6 0 0.5 1.0 1.5 2.0 2.6 2.8 2.5 3.0 kHz 3.5
f
Figure 17
Semiconductor Group
49
1997-07-01
PEB 2265
Transmission Characteristics 5.2.3
.
Group Delay Distortion receive: Input signal level 0dBm01)
ITD09999
500 s tG 400 300 200 150 100 0
85 0.6 0 0.5 1.0 1.5 2.0 2.6 2.8 2.5 3.0 kHz 3.5
f
Figure 18 5.3 Out-of-Band Signals at Analog Input
With an 0 dBm0 out-of-band sine wave signal with frequency f (<<100 Hz or 3,4 kHz to 100 kHz) applied to the analog input, the level of any resulting frequency component at the digital output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog input.2)
1)
2)
HPR is switched on: reference point is at tGmin HPR is switched off: reference point is at 1.5 kHz Poles at 12 kHz 150 Hz and 16 kHz 150 Hz are be provided
Semiconductor Group
50
1997-07-01
PEB 2265
Transmission Characteristics
ITD09998
40 dB 35 32 30
Transmit OUT of Band Discrimination X
25 20 15 10
0
0
0.06 0.1
3.4
4
4.6
6
10
18 kHz 100
f
Figure 19 4000 - F 3.4 ... 4.0 kHz: X = - 14 sin x ---------------------- - 1 1200 4000 - F 7 4.0 ... 4.6 kHz: X = - 18 sin x ---------------------- - -- 1200 9 5.4 Out-of-Band Signals at Analog Output
With a 0 dBm0 sine wave with frequency f (300 Hz to 3.99 kHz) applied to the digital input, the level of any resulting out-of-band signal at the analog output will stay at least X dB below a 0 dBm0, 1 kHz sine wave reference signal at the analog output.
60 dB 50
ITD09997
57
Receive OUT of Band Discrimination X
40 35 30 20 15 10 0 0
28
0.06 0.1
3.4
4
4.6
6
8
10 10.55
16 18 kHz 100
f
Figure 20 4000 - F 3.4 ... 4.6 kHz: X = - 14 sin x ---------------------- - 1 1200
Semiconductor Group 51 1997-07-01
PEB 2265
Transmission Characteristics 5.5 Out of Band Idle Channel Noise at Analog Output
With an idle code applied to the digital input, the level of any resulting out-of-band power spectral density (measured with 3 kHz bandwidth) at the analog output, will be not greater than the limit curve shown in the figure below.
SICOFI -4
R
-40 dBm0 -50 -55 -60 -70 -78 -80 -90 -100 101 10 2 10 3
ITD09996
kHz
10 4
f
Figure 21 5.6 Overload Compression measured with sine wave f = 1014 Hz.
ITD09995
-law, transmit:
10 dBm0 8 7 6 5 4 3 2 1 0.25 0 -0.25 -1
Fundamental Output Power
0
1
2
3
4
5
6
7
dBm0
9
Fundamental Input Power
Figure 22
Semiconductor Group
52
1997-07-01
PEB 2265
Transmission Characteristics 5.7 Gain Tracking (receive or transmit)
The gain deviations stay within the limits in the figures below Gain Tracking:
2 dB G 1.4 1 0.5 0.25 0 -0.25 -0.5 -1 -1.4 -2 -70 -60 -55 -50 -40 -37 -30 -20 Input Level -10 3 0 dBm0 10
(measured with sine wave f = 1014 Hz, reference level is 0 dBm0)
ITD09994
Figure 23 5.8 Total Distortion
The signal to distortion ratio exceeds the limits in the following figure. 5.8.1 Total Distortion Measured with Sine Wave measured with sine wave f = 1014 Hz. (C-message weighted for -law, psophometricaly weighted for A-law)
Receive or Transmit:
Figure 24
Semiconductor Group 53 1997-07-01
PEB 2265
Transmission Characteristics 5.8.2 Receive Total Distortion Measured with Noise According to CCITT
Figure 25 Transmit
Figure 26
Semiconductor Group
54
1997-07-01
PEB 2265
Transmission Characteristics 5.9 Single Frequency Distortion
An input signal with its frequency swept between 0.3 to 3 kHz for the receive path, or 0 to 12 kHz for the transmit path, any generated output signal with other frequency than the input frequency will stay 28 dB below the maximum input level of 0 dBm0. Table 10 Receive Frequency 300 Hz to 3.4 kHz 5.10 Max. Input Level 0 dBm0 Frequency 0 to 12 kHz Transmit Max. Input Level 0 dBm0
Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain and group delay - deviations inherent to the IOM-2 - SICOFI-2 A/D- and D/A-converters as well as to all external components used on a line card (SLIC, OP' s etc.) Measurement of IOM-2 - SICOFI-2 transhybrid-loss: A 0 dBm0 sine wave signal and a frequency in the range between 300 - 3400 Hz is applied to the digital input. The resulting analog output signal at pin VOUT is directly connected to VIN, e.g. with the IOM-2 - SICOFI-2 testmode "Digital Loop Back via Analog Port". The programmable filters FRR, AR, FRX, AX and IM are disabled, the balancing filter TH is enabled with coefficients optimized for this configuration (VOUT = VIN). The resulting echo measured at the digital output is at least X dB below the level of the digital input signal as shown in the table below (Filter coefficients will be provided). Table 11 Parameter Symbol Limit Values min. Trans Hybrid Loss at 300 Hz Trans Hybrid Loss at 500 Hz THL300 THL500 27 33 29 27 27 typ. 40 45 40 35 35 dB dB dB dB dB Unit Test Condition
Trans Hybrid Loss at 2500 Hz THL2500 Trans Hybrid Loss at 3000 Hz THL3000 Trans Hybrid Loss at 3400 Hz THL3400
TA = 25 C; VDD = 5 V TA = 25 C; VDD = 5 V TA = 25 C; VDD = 5 V TA = 25 C; VDD = 5 V TA = 25 C; VDD = 5 V
The listed values for THL correspond to a typical variation of the signal amplitude and -delay in the analog blocks. amplitude delay = typ. 0.15 dB = typ. 0.5 s
Semiconductor Group
55
1997-07-01
PEB 2265
Electrical Characteristics 6 6.1 Table 12 Parameter VDD referred to GNDD GNDA to GNDD Analog input and output voltage referred to VDD = 5 V; referred to GNDA = 0 V All digital input voltages referred to GNDD = 0 V; (VDD = 5 V) referred to VDD = 5 V; (GNDD = 0 V) DC input and output current at any input or output pin (free from latch -up) Storage temperature Power dissipation (package) TSTG PD - 60 - 10 Ambient temperature under bias TA Symbol Limit Values min. - 0.3 - 0.6 - 5.3 - 0.3 - 0.3 - 5.3 max. 7.0 0.6 0.3 5.3 5.3 0.3 10 Unit Test Condition V V V V V V mA Electrical Characteristics Absolute Maximum Ratings
125 80 1
C C W
Semiconductor Group
56
1997-07-01
PEB 2265
Electrical Characteristics 6.2 Operating Range
TA = 0 to 70 C; VDD = 5 V 5 %; GNDD = 0 V; GNDA = 0 V Table 13 Parameter VDD supply current standby operating (2 channels) Power supply rejection of either supply/direction receive VDD guaranteed receive VDD target value Power dissipation standby PDS Power dissipation operating Power dissipation operating 6.3 PDo1 PDo2 Symbol IDD 1.2 27 2 40 mA mA Ripple: 0 to 150 kHz, 70 mVrms Measured: 300 Hz to 3.4 kHz Measured: at f: 3.4 to 150 kHz 1 channel operating 2 channels operating Limit Values min. typ. max. Unit Test Condition
PSRR
30 14 30 15 75 100 20 110 140 dB dB dB mW mW mW
Digital Interface
TA = 0 to 70 C; VDD = 5 V 5 %; GNDD = 0 V; GNDA = 0 V All input-pins, with exception of the RESET-pin, have a TTL-input characteristic. Table 14 Parameter Low-input voltage High-input voltage Low-output voltage Symbol VIL VIH VOL Limit Values min. - 0.3 2.0 0.45 0.45 4.4 1 max. 0.8 V V V V V A IO = - 5 mA IO = - 7 mA, RL = 1 k I0 = 5 mA - 0.3 VIN VDD Unit Test Condition
Low-output voltage DU pin VOL High-output voltage Input leakage current VOH IIL
Semiconductor Group
57
1997-07-01
PEB 2265
Electrical Characteristics 6.4 Analog Interface
TA = 0 to 70 C; VDD = 5 V 5 %; GNDD = 0 V; GNDA = 0 V Table 15 Parameter Analog input resistance Analog output resistance Analog output load Input leakage current Input voltage range (AC) Symbol min. RI RO RL CL IIL VIR 20 20 0.1 1.0 160 Limit Values typ. 270 max. 480 10 k W k pF A 0 VIN VDD Unit Test Condition
V 2.223.
6.5
RESET Timing
To reset the IOM-2 - SICOFI-2 to basic setting mode, positive pulses applied to pin RS have to be higher than 2.4 V (CMOS-Schmitt-Trigger Input) and longer than 3 s. Signals shorter than 1 s will be ignored.
Semiconductor Group
58
1997-07-01
PEB 2265
Electrical Characteristics 6.6 6.6.1 IOM(R)-2 Interface Timing 4-MHz Operation Mode (Mode = 1)
t DCL
90% DCL 10%
t DCLh
t FSC_S
FSC
t FSC_H
t FSC
t DD_S
DD
t DD_H
t dDU
DU
t dDUhz
High Imp.
ITD03389
Figure 27 Switching Characteristics Table 16 Parameter Period DCL `fast' mode 1) DCL duty cycle Period FSC 1) FSC setup time FSC hold time DD data in setup time DD data in hold time DU data out delay 2)
1) 2)
Symbol min. tDCL 40 tFSC tFSC_S tFSC_H tDD_S tDD_H tdDU 70 40 20 50
Limit Values typ. 1/4096 60 125 tDCLh max.
Unit kHz % s ns ns ns ns
150
320
ns
DCL = 4096 kHz: tFSC = 512 x tDCL Depending on Pull-up resistor used in application (typical 1 k), DU is a "open drain" - line
Semiconductor Group
59
1997-07-01
PEB 2265
Electrical Characteristics 6.6.2 2-MHz Operation Mode (Mode = 0)
t DCL
DCL
t DCLh
t FSC t FSC_S
FSC
t FSC_H
t DD_S t DD_H
DD
t dDU
DU
t dDUhz
High Imp.
ITD09993
Figure 28 Switching Characteristics Table 17 Parameter Period DCL "slow" mode1) DCL duty cycle Period FSC
1)
Symbol min. tDCL 40 tFSC tFSC_S tFSC_H tDD_S tDD_H tdDU 70 40 20 50
Limit Values typ. 1/2048 60 125 tDCLh max.
Unit kHz % s ns ns ns ns
FSC setup time FSC hold time DD data in setup time DD data in hold time DU data out delay2)
1) 2)
150
175
ns
DCL = 2048 kHz: tFSC = 256 x tDCL Depending on pull up resistor used in application (typical 1 k), DU is a "open drain" - line.
Semiconductor Group
60
1997-07-01
PEB 2265
Electrical Characteristics 6.7 6.7.1 IOM(R)-2 Command/Indication Interface Timing 4-MHz Operation Mode (Mode = 1)
Figure 29
Semiconductor Group
61
1997-07-01
PEB 2265
Electrical Characteristics 6.7.2 2-MHz Operation Mode (Mode = 0)
Figure 30 Switching Characteristics Table 18 Parameter Command out delay Command out high impedance Command out active Indication in setup time Indication in hold time Symbol min. tdCout tdCZ tdCA tlin_s tlin_h
62
Limit Values typ. 150 150 150 50 100 max. 250 250 250
Unit ns ns ns ns ns
Semiconductor Group
1997-07-01
PEB 2265
Electrical Characteristics 6.8 Detector Select Timing
Figure 31 6.8.1 Table 19 Parameter Detector select high time Detector select repeat Indication in setup time Indication in hold time Symbol min. tLGKMh tLGKM tlin_s tlin_h
63
Switching Characteristics
Limit Values typ. 125 1 ... 14 50 100 max.
Unit s ms ns ns
Semiconductor Group
1997-07-01
PEB 2265
Appendix 7 7.1 7.1.1 Appendix IOM(R)-2 Interface Monitor Transfer Protocol Monitor Channel Operation
The Monitor Channel is used for the transfer of maintenance information between two functional blocks. Using two monitor control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. The MR and MX bits in the fourth octet (C/I channel) of the IOM-2 frame are used for the handshake procedure of the monitor channel. The monitor channel transmission operates on a pseudo-asynchronous basis: - Data transfer (bits) on the bus is synchronized to Frame Sync FSC - Data flow (bytes) are asynchronously controlled by the handshake procedure. For example: Data is placed onto the DD-monitor-channel by the monitor-transmitter of the master device (DD-MX-Bit is activated i.e. set to `0'). This data transfer will be repeated within each frame (125 s rate) until it is acknowledged by the IOM-2 - SICOFI-2 monitor-receiver by setting the DU-MR-bit to `0', which is checked by the monitor-transmitter of the master device. Thus, the data rate is not 8 kbyte/s.
Figure 32
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Appendix 7.1.2 Monitor Handshake Procedure
The monitor channel works in 3 states A pair of inactive (set to `1') MR- and MX-bits during two or more consecutive frames: End of Message (EOM) - sending state: MX-bit is activated (set to `0') by the monitor-transmitter, together with data-bytes (can be changed) on the monitor-channel - acknowledging: MR-bit is set to active (set to `0') by the monitor-receiver, together with a data-byte remaining in the monitor-channel. A start of transmission is initiated by a monitor-transmitter in sending out an active MX-bit together with the first byte of data (the address of the receiver) to be transmitted in the monitor-channel. This state remains until the addressed monitor-receiver acknowledges the received data by sending out an active MR-bit, which means that the data-transmission is repeated each 125 s frame (minimum is one repetition). During this time the monitor-transmitter evaluates the MR-bit. Flow control, means in the form of transmission delay, can only take place when the transmitters MX and the receivers MR bit are in active state. Since the receiver is able to receive the monitor data at least twice (in two consecutive frames), it is able to check for data errors. If two different bytes are received the receiver will wait for the receipt of two identical successive bytes (last look function). A collision resolution mechanism (check if another device is trying to send data during the same time) is implemented in the transmitter. This is done by looking for the inactive (`1') phase of the MX-bit and making a per bit collision check on the transmitted monitor data (check if transmitted `1's are on DU/DD-line; DU/DD-line are open-drain lines). Any abort leads to a reset of the IOM-2 - SICOFI-2 command stack, the device is ready to receive new commands. To obtain a maximum speed data transfer, the transmitter anticipates the falling edge of the receivers acknowledgment. Due to the inherent programming structure, duplex operation is not possible. It is not allowed to send any data to the IOM-2 - SICOFI-2, while transmission is active. - idle state:
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Appendix 7.1.3 State Diagram of the IOM(R)-2 - SICOFI(R)-2 Monitor Transmitter
MR + MXR MXR Idle MX = 1 MR. MXR Wait MX = 1 MR. MXR Abort MX = 1
Initial State
MR. RQT
MR
1st Byte MX = 0
MR. RQT
EOM MX = 1
MR
MR. RQT
nth Byte ACK MX = 1
MR
MR
MR. RQT
Wait for ACK MX = 0
MR. RQT
CLS/ABT Any State
ITD02458
Figure 33 MR ... MX ... MXR ... CLS ... RQT ... ABT ... MR - bit received on DD - line MX - bit calculated and expected on DU - line MX - bit sampled on DU - line Collision within the monitor data byte on DU - line Request for transmission form internal source Abort request/indication logical AND logical OR
66 1997-07-01
....
+...
Semiconductor Group
PEB 2265
Appendix 7.1.4 State Diagram of the IOM(R)-2 - SICOFI(R)-2 Monitor Receiver
Idle MR = 1
MX .LL
MX
Initial State
MX
1st Byte REC MR = 0
MX
Abort MR = 1 ABT
MX
MX
MX
Any State Wait for LL MR = 0
MX
Byte Valid MR = 0
MX . LL
MX .LL
MX
MX
MX . LL
MX .LL
New Byte MR = 1
nth Byte REC MR = 1
MX .LL
Wait for LL MR = 0
ITD02459
Figure 34 MR ... MX ... LL ... ABT ... .... +... MR - bit calculated and transmitted on DU - line MX - bit received data downstream (DD - line) Last lock of monitor byte received on DD - line Abort indication to internal source logical AND logical OR
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Appendix 7.2 Monitor Channel Data Structure
The monitor channel is used for the transfer of maintenance information between two functional blocks. By use of two monitor control bits (MR and MX) per direction, the data are transferred in a complete handshake procedure. 7.2.1 Address Byte
Messages to and from the IOM-2 - SICOFI-2 are started with the following Monitor byte: Bit 7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 1
Thus providing information for two voice channels, the IOM-2 - SICOFI-2 is one device on one IOM-2 time slot. Monitor data for a specific voice channel is selected by the IOM-2 - SICOFI-2 specific command (SOP or COP). 7.2.2 Identification Command
In order to be able to unambiguously identify different devices by software, a two byte identification command is defined for analog lines IOM-2 devices. 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Each device will then respond with its specific identification code. For the IOM-2 - SICOFI-2 this two byte identification code is: 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Each byte is transferred at least twice (in two consecutive frames).
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Appendix 7.3 IOM(R)-2 Interface Programming Procedure
Example for a typical IOM-2 interface programming procedure, consisting of identification request and answer, a SOP Write command with three byte following, and SOP Read to verify the programming. Table 20 Frame Monitor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 11111111 IDRQT. 1st byte IDRQT. 1st byte IDRQT. 2nd byte IDRQT. 2nd byte 11111111 11111111 11111111 11111111 11111111 11111111 Address Address SOP Write SOP Write CR3 CR3 CR2 CR2 CR1 CR1 SOP Read SOP Read 11111111 11111111 Data Down MR/MX 11 10 10 11 10 11 11 01 01 11 01 10 10 11 10 11 10 11 10 11 10 11 10 11 11 Monitor 11111111 11111111 11111111 11111111 11111111 11111111 IDANS. 1st byte IDANS. 1st byte IDANS. 2nd byte IDANS. 2nd byte 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 Address Data Up MR/MX 11 11 01 01 11 01 10 10 11 10 11 11 01 01 11 01 11 01 11 01 11 01 11 01 10
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Appendix Table 20 Frame Monitor 26 27 28 29 30 31 32 33 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 (cont'd) Data Down MR/MX 01 01 11 01 11 01 11 01 Monitor Address CR3 CR3 CR2 CR2 CR1 CR1 11111111 Data Up MR/MX 10 11 10 11 10 11 10 11
IDRQT ... identification request (80H, 00H) IDANS ... answer to identification request (80H, 82H) Address ... IOM-2 - SICOFI-2 specific address byte (81H) CRx ... Data for/from configuration register x.
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Test Features 8 8.1 8.1.1 Test Features Boundary Scan General
The IOM-2 - SICOFI-2 provides fully IEEE Std. 1149.1 compatible boundary scan support consisting of: - - - - a complete boundary scan (digital pins) a test access port controller (TAP) four dedicated pins (TCK, TMS, TDI, TDO) a 32 bit ICODE register
All IOM-2 - SICOFI-2 digital pins expect power supply VDD D and ground GNDD are included in the boundary scan. Depending on the pin functionality one, two or three boundary cells are provided. Table 21 Pin Type Input Output I/O Number of Boundary Scan Cells 1 2 3 Usage Input Output, enable Input, output, enable
When the TAP controller is in the appropriate mode, data is shifted into/out of the boundary scan via the pins TDI/TDO controlled by the clock applied to pin TCK. The IOM-2 - SICOFI-2 pins are included in the following sequence in the boundary scan: Table 22 Pin Number 57 59 60 61 62 63 64 1
Semiconductor Group
Pin Name MODE TSS1 TSS0 N.U.I. N.U.I. N.U.I. N.U.IO. N.U.IO.
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Type I I I I I I I/O I/O
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Test Features Table 22 2 3 4 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 45 46 47 48 (cont'd) Pin Name N.C. N.C. N.C. N.C. N.C. N.C. N.U.IO. N.U.IO. N.U.I. N.U.I. N.U.I. N.C. RESET DD DU DCL FSC LGKM0 SI1_2 SI1_1 SI1_0 SB1_1 SB1_0 SO1_2 SO1_1 SO1_0 SO2_0 SO2_1 SO2_2 SB2_0 Type O O O O O O I/O I/O I I I O I I O (open drain) I I O I I I I/O I/O O O O O O O I/O
Pin Number
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Test Features Table 22 49 50 51 52 8.1.2 (cont'd) Pin Name SB2_1 SI2_0 SI2_1 SI2_0 The TAP-Controller Type I/O I I I
Pin Number
The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE Std. 1149.1. Transitions on pin TMS (Test Mode Select) cause the TAP controller to perform a state change. According to the standard definition five instructions are executable:
Figure 35
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Test Features Table 23 Code 0000 0001 0010 0011 0100 0101 1000 0111 11xx EXTEST INTEST Instruction EXTEST INTEST SAMPLE/PRELOAD ICODE Tap_Test 1 Tap_Test 2 Tap_Test 5 Tap_Test 4 BYPASS Function External testing Internal testing Snap-shot testing Reading ID code Configuration for Level Metering Wait for result Serial testdata output (Level Metering Results) Switch off Test Bypass operation
Is used to examine the board interconnections. Supports internal chip testing (is the default value of the instruction register)
SAMPLE/PRELOAD Provides a snap-shot of the pin level during normal operation, or is used to preload the boundary scan with a test vector ICODE The 32 bit identification register is serially read out via TDO. It contains a version number (4 bit), a device code (16 bit) and the manufacture code (11 bit). The LSB is fixed to `1'. For the IOM-2 - SICOFI-2 V1.1 the Code is: `0011 0000 0000 0001 0101 0000 1000 001 1' 39 bit field for selecting operation (Level Metering Offset, Loops, Tone Generator ...) Wait for Level Metering result ready (should be > t.b.d. mS) Level Metering Data output (1 bit result of Level Metering per channel) Level Metering Operation is switched off a bit entering TDI is shifted to TDO after one TCK clock cycle
TAP_TEST1 TAP_TEST2 TAP_TEST5 TAP_TEST4 BYPASS
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Test Features 8.2 Level Metering Function
The Level Metering Function is a functional selftest (available per channel), which allows selftest of the chip (digital, or digital and analogue), and also selftest of the board (including the SLIC). An external or internally generated sine-wave signal is fed to the receive path. After switching a loop (internal or external via the SLIC) to the transmit-path the return level is measured and compared to a programmable offset value. The result of this operation (greater or smaller than offset) can be read out via the IOM-2 interface (bit LMR in configuration register CR2). There is a single-8-bit Offset-Register available for both two channels. This offset register can be accessed as XR4 with a XOP-Command (Field LSEL = 100) This register contains the 2's complement offset value for the level metering function Bit 7 OF7 Block Diagram 6 OF6 5 OF5 4 OF4 3 OF3 2 OF2 1 OF1 0 OF0
Offset Config.Register
ABS Transmit Path Sign
x
A-B
LMR
LM
FRX* AX1* HPX CMP PCMOUT
VIN
AGX
ADC
DSI
DS2
AX2*
*programmable
IM2* IM1* TH* TG1,2
VOUT
AGR
DAC
+
US2
R1*
US1
AR2*
FRR*
AR1*
HPR*
EXP
PCMIN
Receive Path
iom36.wmf
Figure 36 (For further information, an Application Note describing the calculation of the offset value and the sensitivity, is available).
Semiconductor Group
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Test Features 8.3 Programming the IOM(R)-2 - SICOFI(R)-2 Tone Generators
Two independent Tone Generators are available per channel. When one or both tone-generators are switched on, the voice signal is switched off automatically for the selected voice channel. To make the generated signal sufficient for DTMF, a programmable bandpass-filter is included. The default frequency for both tone generators is 1000 Hz. The QSICOS-program contains a program for generating coefficients for variable frequencies. Byte sequences for programming both the tone generators and the bandpass-filters: Table 24 Frequency 697 Hz 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 800 Hz 950 Hz 1008 Hz 2000 Hz
1)
Command 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D1) 0C/0D
1) 1)
Byte 1 0A 12 13 1D 32 EC AA 12 1C 1A 00
Byte 2 33 33 3C 1B 32 1D AC D6 F0 AE 80
Byte 3 5A 5A 5B 5C 52 52 51 5A 5C 57 50
Byte 4 2C C3 32 CC B3 22 D2 C0 C0 70 09
0C/0D
0C/0D1)
0C is used for programming Tone Generator 1, in channel 1. 0D is used for programming Tone Generator 2, in channel 1.
The resulting signal amplitude can be set by transmitting the AR1 and AR2 filters. By switching a "digital loop" the generated sine-wave signal can be fed to the transmit path.
Semiconductor Group
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Package Outlines 9 Package Outlines P-MQFP-64-1-2 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 77
Dimensions in mm 1997-07-01
GPM05250

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